In the packaging of integrated circuits, particular flip chip packaging, warpage and stress are generated due to the mismatch in Coefficients of Thermal Expansion (CTEs) between different materials and different package components. The warpage and stress are major concerns in the improvement in the reliability of package structures.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved flip chip package that overcomes the problems discussed above.